A high-resolution clock phase shifter circuitry for ALTIROC

Abstract A high-resolution clock phase shifter is implemented to adjust the of multiple clocks at 40 MHz, 80 or 640 MHz in ALTIROC chip. The has a coarse-phase and fine-phase achieve step size 97.7 ps an adjustable range 25 ns. fine delay unit based on Delay Locked Loop (DLL) operating MHz. fabricated 130 nm CMOS process. area 725 µm × 248 µm. Differential Non-Linearity (DNL) Integral (INL) are ±0.6 LSB ±0.75 LSB, respectively. jitter from −25 °C 20 less than 15.5 (RMS), including contributions FPGA source PLL. power consumption 11.2 mW.